Job Description

LEAD PROJECT ENGINEER - ASIC & SoC

“Exceptional opportunity for an impact player to join a talented team in a key customer facing role within high growth design department.  Hands on ASIC project engineering experience, micro architecture, AMBA protocols and verification development cycle expertise a prerequisite.”

US $ 160-200,000 (DOE) + Bonus & Excellent Benefits

California – US Citizens or Visa Sponsorship/Transfer for Exceptional International Talent Residing in US Currently

Our client is a $multibillion, global, innovative enterprise that designs, develops and delivers System-on-Chip based solutions to customers worldwide. The company is focused on technologies that drive today’s leading-edge applications in consumer, automotive and industrial markets. Our client combines world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers.
As a result of dynamic growth and increased demand, our client seeks to strengthen its team with the appointment of an experienced, highly customer focused, Lead Project Engineer.  This is a unique opportunity in a key customer interface role within a high growth design department focused on ASIC and SoC. You will be part of a team delivering silicon solutions to some of the world’s biggest brands.

The Role:
As Lead Project engineer you will take a fully hands on technical customer interfacing approach to project engineering and will work closely with verification and ASIC development teams as well as customers.  Our client offers true autonomy to solely lead and drive projects.
You will be experienced in leading and driving ASIC and SoC project engineering projects, providing technical leadership whilst also ensuring that the team delivers final silicon designs from R & D to the customer.  Therefore, to succeed in this role you must have extensive customer liaison and relationship building skills gained within a SoC services organisation.  This must be combined with ASIC design and verification (UVM) knowledge; the ability to perform some hands-on verification activities yourself and an impressive track record of delivering silicon solutions from front end to tape out.  
Specifically, you will:
•    Lead projects that are currently in the advanced stages of the sales pipeline
•    Work with ASIC customers to define die-size, floor plan, architectural exploration of timing feasibility, support IP handling from a physical design standpoint and help with integration of full chip timing constraints
•    Work and liaise with other Design and Verification teams within customer sites to identify gaps in the design verification flow and implement corrective action
•    In-depth knowledge of design and verification and be able to provide feedback to the design team
•    Work closely with the design team to ensure that the company is meeting project design requirements.  This may include review of specifications, understanding chip architecture, developing tests and coverage plans and defining methodology and test benches
•    Work closely with Custom SoC department to provide great customer service to our clients and projects at hand.  
•    Support, encourage and drive timely and accurate deliverables with customers within schedules
•    You will be part of a team delivering silicon solutions to some of the world’s biggest brands.
The Ideal Profile:
•    Educated to BS or MS in Computer Science or Electrical Engineering
•    Minimum 6 years plus in ASIC Front End and physical design in a SoC organisation
•    Demonstrable experience of the complete RTL2GDSII design flow with multiple tapeout experience in 28nm/16nm/7nm process technologies is preferred
•    You must have extensive customer liaison experience gained within a SoC services organisation, ASIC Design and verification (UVM) knowledge; the ability to perform some hands-on verification activities and a track record of delivering silicon solutions from front end to tape out
•    Hands on experience with implementation EDA tools such as Genus/DC, Innovus/ICC2 and sign off tools like Voltus/Redhawk, Tempus/PrimeTime and ICV is a must
•    Functional understanding of constrained random verification (UVM), functional coverage and code coverage
•    Functional understanding of clock domain crossings, lint/cdc checks, SDC, leading protocols such as PCIe, USB, MIPI, experience with embedded CPUs
•    Experience must have been gained within a ASIC/SoC services company desired
•    Dynamic growth SME experience would be a perfect cultural fit for our client
•    International experience especially working with APAC and Japanese markets and customers

To apply without delay please email your CV in confidence quoting reference LX 498712 to applications@martinveasey.com  Telephone 00 44 (0) 1905 381 320